a. The FETCH phase of the instruction cycle does two important things. One is that it loads the instruction to be processed next into the IR. What is the other important thing?
b. Examples 4.1, 4.2, and 4.5 illustrate the processing of the ADD, LDR, and JMP instructions. The PC, IR, MAR, and MDR are written in various phases of the instruction cycle, depending on the opcode of the particular instruction. In each location in the table below, enter the opcodes which write to the corresponding register (row) during the corresponding phase (column) of the instruction cycle.
Example 4. 1:
The ADD Instruction The ADD instruction requires three operands: two source operands (the data that is to he added) and one destination operand (the sum that is to be stored after the addition is performed). We said that the processing unit of the LC-3 contained eight registers for purposes of storing data that may be needed later. In fact, the ADD instruction requires that at least one of the two source operands (and often both) is contained in one of these registers, and that the result of the ADD is put into one of these eight registers. Since there are eight registers, three hits are necessary to identify each register. Thus the 16-bit LC-3 ADD instruction has the following form (we say format):
The 4-hii opcode lor ADD. contained in hits 115:121. is 0001. Hits 11identif y the location Lo he used for storing ihe result, in this case register 6 (R6). Bits |K:ft| and hits 12:0| identify the regislers lo he used lo obtain Ihe source operands, in this case R2 and Rft. Mils 15:31 have a purpose that it is not necessary lo understand in the context of this example. We will save Ihe explanation of hils [5:31 for Section 5.2. Thus, the instruction we have just encoded is interpreted, “Add the contents of register 2 (R2) to the contents of register 6 (Rft) and store the result back into register 0(K6i;
Example 4.2:
The LDR Instruction The LDR instruction requires two operands. LD stands for load, which is computerese for “go to a particular memory location, read the value that is contained there, and store it in one of the registers.” The two operands that are required are the value to be read from memory and the destination register, which will contain that value after the instruction is processed. The R in LDR identifies the mechanism that will be used to calculate the address of the memoiy location to be read. That mechanism is called the addressing mode, and the particular addressing mode identified by the use of the letter R is called Base+offset. Thus, the 16-bit LC-3 LDR instruction has the following format:
The four-bit opcode for LDR is 0110. Bits [11:9) identify the register that will contain the value read from memory after the instruction is executed. Bits [8:0] are used to calculate the address of the location to be read. In particular, since the addressing mode is BASE+offset, this address is computed by adding the 2's complement integer contained in bits [5:0| of the instruction to the contents of the register specified by bits 18:6]. Thus, the instruction we have just encoded is interpreted: “Add the contents of R3 to the value 6 to form the address of a memory location. Load the contents stored in that memory location into R2.”
Example 4.5:
The JM P Instruction Considerthe LC-3 instruction JMP, whose formal follows. Assume lliis instruction is stored in memory location x36A2.
The 4-bit opcode for JMP is I KM). Hits |8:ft| specify the register which contains the address of the next instruction to be processed. Thus, the instruction encoded here is interpreted, “I ,oad the PC (during the HXliCUTL phase) with the contents of R3 so that the next instruction processed will be the one at the address obtained from R3.”
Processing will go on as follows. I,efs start at the beginning of the instruction cycle, with PC = X.16A2. The FETCH phase results in the IK being loaded with the JMP instruction and the PC updated to contain the address x36A3. Suppose the content of R3 at the start of this instruction is x5446. During the KXIiCUTK phase, the PC is loaded with x5446. Therefore, in the next instruction cycle, the instruction processed will be the one at address x5446. rather than the one at address x36A3.